// FPGAControl.h: interface for the FPGAControl class. // ////////////////////////////////////////////////////////////////////// #if !defined( __FPGACONTROL_H__ ) #define __FPGACONTROL_H__ #if defined(WIN32) #if _MSC_VER >= 1000 #pragma once #endif // _MSC_VER >= 1000 #endif // win32 #include "VXIVMEControl.h" #define BUSY 0x10000 #define HST_BUSY 0x03000 #define DAC_BUSY 0x04000 #define TV_BUSY 0x08000 #define TVDIFF 0x20000 #define FIFOEMPTY 0x20000 #define ENDFLAG 0x20000 #define ALLCHIPS 0x3f // limits #define FREQMIN 25 #define FREQMAX 133 #define CLK0_width 0x78 #define CLK0_delay 0x79 #define CLK1_width 0x7A #define CLK1_delay 0x7B #define COM0_width 0x7c #define COM0_delay 0x7d #define COM1_width 0x7e #define COM1_delay 0x7f #define TOKENIN0_width 0x70 #define TOKENIN0_delay 0x71 #define TOKENIN1_width 0x72 #define TOKENIN1_delay 0x73 #define DATAIN0_width 0x74 #define DATAIN0_delay 0x75 #define DATAIN1_width 0x76 #define DATAIN1_delay 0x77 #define VCC_dac 0x6a #define VDD_dac 0x6b #define CLK0 0x60 #define CLK0_high 0x60 #define CLK0_low 0x61 #define CLK0_B 0x62 #define CLK0B_high 0x62 #define CLK0B_low 0x63 #define CLK1 0x64 #define CLK1_high 0x64 #define CLK1_low 0x65 #define CLK1_B 0x66 #define CLK1B_high 0x66 #define CLK1B_low 0x67 #define COM0 0x58 #define COM0_high 0x58 #define COM0_low 0x59 #define COM0_B 0x5a #define COM0B_high 0x5a #define COM0B_low 0x5b #define COM1 0x5c #define COM1_high 0x5c #define COM1_low 0x5d #define COM1_B 0x5e #define COM1B_high 0x5e #define COM1B_low 0x5f #define TOKENIN0 0x50 #define TOKENIN0_high 0x50 #define TOKENIN0_low 0x51 #define TOKENIN0_B 0x52 #define TOKENIN0B_high 0x52 #define TOKENIN0B_low 0x53 #define TOKENIN1 0x54 #define TOKENIN1_high 0x54 #define TOKENIN1_low 0x55 #define TOKENIN1_B 0x56 #define TOKENIN1B_high 0x56 #define TOKENIN1B_low 0x57 #define DATAIN0 0x48 #define DATAIN0_high 0x48 #define DATAIN0_low 0x49 #define DATAIN0_B 0x4a #define DATAIN0B_high 0x4a #define DATAIN0B_low 0x4b #define DATAIN1 0x4c #define DATAIN1_high 0x4c #define DATAIN1_low 0x4d #define DATAIN1_B 0x4e #define DATAIN1B_high 0x4e #define DATAIN1B_low 0x4f #define LED_thr 0x40 #define LED_thr_high 0x40 #define LED_thr_low 0x41 #define DATAOUT0 0x42 #define DATAOUT0_thr_high 0x42 #define DATAOUT0_thr_low 0x43 #define DATAOUT1 0x44 #define DATAOUT1_thr_high 0x44 #define DATAOUT1_thr_low 0x45 #define TOKENOUT0 0x46 #define TOKENOUT0_thr_high 0x46 #define TOKENOUT0_thr_low 0x47 #define TOKENOUT1 0x38 #define TOKENOUT1_thr_high 0x38 #define TOKENOUT1_thr_low 0x39 #define ADC_Vcc 0 #define ADC_Vdd 1 #define ADC_Temp 2 #define ADC_Ip 3 #define ADC_Ish 4 #define ADC_Vt 5 #define ADC_Icc 6 #define ADC_Idd 7 class DLLSPEC FPGAControl : public VXIVMEControl { public: FPGAControl(unsigned int); virtual ~FPGAControl(); // Attributes public: long QueryBoard(unsigned long msk=0xffffffff); int ResetTVMem(); int ResetSimMem(); int ClearHistoMem(); unsigned long ReadHistoMem(); int LoadHistoBaseAddr(long address); int SendTV(); int SendTVnowait(); int WriteTVMem(long value); int WriteSimMem(long value); int ResetOutFIFO(); int SetDAC(int DACaddress, int value); long ReadADC(int ADCaddress, int byPassWait = 0); int StartADCConversion(int ADCaddress, int byPassWait =0); long ReadADCValue(int byPassWait = 0); long ReadOutFIFO(); int SendTriggers(); int LoadTriggerNum(long triggerNum); int LoadTrigSpacing(long spacing); int EnableStrobe(); int DisableStrobe(); int EnableInpRegPulse(); int DisableInpRegPulse(); int SetFreq(float freq); int SetFreq(long nvalue, long mvalue); int SetFreq(long tvalue, long nvalue, long mvalue); int LoadStrobe2TrigDelay(long delay); int LoadTestVector(const char *); int LoadSimVector(const char *); int LoadTunedSimVector(long *, int); int TVDiffLocation(); int TVDiffWord(); int ResetOutResyncFIFO(); void SetDACs(); void SetDACs(float vcc,float vdd, float frequency); void SetThreshold(int lvl, float center, float halfwidth); void SetDelay( int nSig, float value ); void ClearDACs(); int EnablePinDriver(bool); int SetHitMask(int mask_no); int GetDataQualityFlag(); int ReadFirmwareDate(); int SetHeaderDetect( int line_no ); void SetVcc(float x); void SetVdd(float x); void SetChipVoltages(float , float); // Calibration constants void SetClockLatchDAC(float freq); void SetClockLatch(float *); void SetADCConversion( float *v); void SetADCOffset(float *v); float GetClockLatch(int x) const { return clock_latch[x]; } float GetADCConversion(int x) const { return adc_conversion[x]; } float GetADCOffset(int x) const { return adc_offset[x]; } void SetVccScale(float x) { vcc_scale=x; } void SetVddScale(float x) { vdd_scale=x; } float GetVccScale() const { return vcc_scale; } float GetVddScale() const { return vdd_scale; } //wb: use with care.. long GeTPostAccessTimeoutLimit(void); long GeTPreAccessTimeoutLimit(void); long SeTPostAccessTimeoutLimit(long t); long SeTPreAccessTimeoutLimit(long t); protected: volatile UINT32 *_QueryBoard; volatile UINT32 *_ResetTVMem; volatile UINT32 *_ResetSimMem; volatile UINT32 *_ClearHistoMem; volatile UINT32 *_ReadHistoMem; volatile UINT32 *_HistoBaseAddr; volatile UINT32 *_SendTV; volatile UINT32 *_WriteTVMem; volatile UINT32 *_WriteSimMem; volatile UINT32 *_ResetOutFIFO; volatile UINT32 *_SetDAC; volatile UINT32 *_StartConvADC; volatile UINT32 *_ReadADC; volatile UINT32 *_ReadOutFIFO; volatile UINT32 *_SendTrig; volatile UINT32 *_SetFreq; volatile UINT32 *_TrigSpacing; volatile UINT32 *_NumTrig; volatile UINT32 *_SoftReset; volatile UINT32 *_BCReset; volatile UINT32 *_ConfigReg; volatile UINT32 *_ResetMaskReg; volatile UINT32 *_WriteMaskReg; volatile UINT32 *_SendMaskReg; volatile UINT32 *_StrobeDelay; volatile UINT32 *_ThreshCal; volatile UINT32 *_EnableData; volatile UINT32 *_EnableStrobe; volatile UINT32 *_DisableStrobe; volatile UINT32 *_PreampShaper; volatile UINT32 *_LoadTrimDAC; volatile UINT32 *_Strobe2Trig; volatile UINT32 *_TVdiffLoc; volatile UINT32 *_TVdiffWord; volatile UINT32 *_ResetOutResyncFIFO; volatile UINT32 *_enablePinDriver; volatile UINT32 *_setHitMask; volatile UINT32 *_readDataFlags; volatile UINT32 *_readFirmwareDate; volatile UINT32 *_setHeaderDetect; // Calibration constants float clock_latch[4]; float adc_conversion[8]; float adc_offset[8]; float vcc_scale; float vdd_scale; // timeout pre,post access valuse (in ms). long pre_access_timeout ; long post_access_timeout ; long QueryBoardX(unsigned long msk=0xffffffff); }; #define MxTRY 20000 #define VME_WRITE(ptr,busy,who,val) { \ volatile int ntry; \ if ( Lock(MTX_VME) ) \ *log << "** ERROR ** " #who ": Could not get the MuTeX" << endl; \ \ for (ntry=0; (busy) && QueryBoardX((busy)) && ntry= MxTRY) \ *log << "** FATAL ERROR ** " #who ": overrun BUSY flag on entrance " << endl ; \ *(ptr) = (val); \ for (ntry=0; (busy) && QueryBoardX((busy)) && ntry= MxTRY) \ *log << "** FATAL ERROR ** " #who ": overrun BUSY flag on leaving " << endl ; \ \ UnLock(MTX_VME); \ } #define VME_READ(ptr,busy,who,val) { \ volatile int ntry; \ if ( Lock(MTX_VME) ) \ *log << "** ERROR ** " #who ": Could not get the MuTeX" << endl; \ \ for (ntry=0; (busy) && QueryBoardX((busy)) && ntry