// FPGAControl.cpp: implementation of the FPGAControl class.
//
//////////////////////////////////////////////////////////////////////
#include <iostream.h>
#include <fstream.h>
#include "FPGAControl.h"
#ifdef _DEBUG
#undef THIS_FILE
static char THIS_FILE[]=__FILE__;
//#define new DEBUG_NEW
#endif


//////////////////////////////////////////////////////////////////////
// Construction/Destruction
//////////////////////////////////////////////////////////////////////

FPGAControl::FPGAControl(unsigned int addr)
   : VXIVMEControl(addr)
{
   if ( baseAddress ) {
      _QueryBoard    = (volatile UINT32 *)(baseAddress +0x000);
      _ResetTVMem    = (volatile UINT32 *)(baseAddress +0x010);
      _ResetSimMem   = (volatile UINT32 *)(baseAddress +0x020);
      _ClearHistoMem = (volatile UINT32 *)(baseAddress +0x030);
      _ReadHistoMem  = (volatile UINT32 *)(baseAddress +0x040);
      _HistoBaseAddr = (volatile UINT32 *)(baseAddress +0x050);
      _SendTV        = (volatile UINT32 *)(baseAddress +0x060);
      _WriteTVMem    = (volatile UINT32 *)(baseAddress +0x070);
      _WriteSimMem   = (volatile UINT32 *)(baseAddress +0x080);
      _ResetOutFIFO  = (volatile UINT32 *)(baseAddress +0x090);
      _SetDAC        = (volatile UINT32 *)(baseAddress +0x0a0);
      _StartConvADC  = (volatile UINT32 *)(baseAddress +0x0b0);
      _ReadADC       = (volatile UINT32 *)(baseAddress +0x0c0);
      _ReadOutFIFO   = (volatile UINT32 *)(baseAddress +0x0d0);
      _SendTrig      = (volatile UINT32 *)(baseAddress +0x0e0);
      _SetFreq       = (volatile UINT32 *)(baseAddress +0x0f0);

      _TrigSpacing   = (volatile UINT32 *)(baseAddress +0x100);
      _NumTrig       = (volatile UINT32 *)(baseAddress +0x110);
      _SoftReset     = (volatile UINT32 *)(baseAddress +0x120);
      _BCReset       = (volatile UINT32 *)(baseAddress +0x130);
      _ConfigReg     = (volatile UINT32 *)(baseAddress +0x140);
      _ResetMaskReg  = (volatile UINT32 *)(baseAddress +0x150);
      _WriteMaskReg  = (volatile UINT32 *)(baseAddress +0x160);
      _SendMaskReg   = (volatile UINT32 *)(baseAddress +0x170);
      _StrobeDelay   = (volatile UINT32 *)(baseAddress +0x180);
      _ThreshCal     = (volatile UINT32 *)(baseAddress +0x190);
      _EnableData    = (volatile UINT32 *)(baseAddress +0x1a0);
      _EnableStrobe  = (volatile UINT32 *)(baseAddress +0x1b0);
      _DisableStrobe = (volatile UINT32 *)(baseAddress +0x1c0);
      _PreampShaper  = (volatile UINT32 *)(baseAddress +0x1d0);
      _LoadTrimDAC   = (volatile UINT32 *)(baseAddress +0x1e0);
      _Strobe2Trig   = (volatile UINT32 *)(baseAddress +0x1f0);
      _TVdiffLoc     = (volatile UINT32 *)(baseAddress +0x200);
      _TVdiffWord    = (volatile UINT32 *)(baseAddress +0x210);
      _ResetOutResyncFIFO = (volatile UINT32 *)(baseAddress +0x220);
      _enablePinDriver = (volatile UINT32 *)(baseAddress +0x240);
	  _setHitMask    = (volatile UINT32 *)(baseAddress + 0x250);
	  _readDataFlags = (volatile UINT32 *)(baseAddress + 0x260);
	  _readFirmwareDate = (volatile UINT32 *)(baseAddress +0x270);
	  _setHeaderDetect = (volatile UINT32 *)(baseAddress +0x280);
      
   }
   // Calibration constants
   clock_latch[0] = 45.0f;
   clock_latch[1] = 30.4f;
   clock_latch[2] = -1063.0f;
   clock_latch[3] = 0.1187f;

   adc_conversion[ADC_Vcc ] = 1.5f;
   adc_conversion[ADC_Vdd ] = 1.5f;
   adc_conversion[ADC_Temp] = 0.5f/10.f;
   adc_conversion[ADC_Ip  ] = 0.4f; // 
   adc_conversion[ADC_Ish ] = 0.1f;
   adc_conversion[ADC_Vt  ] = 0.5f;
   adc_conversion[ADC_Icc ] = 0.05f;
   adc_conversion[ADC_Idd ] = 0.05f;

   adc_offset[ADC_Vcc ] = 0.;
   adc_offset[ADC_Vdd ] = 0.;
   adc_offset[ADC_Temp] = 0.;
   adc_offset[ADC_Ip  ] = 0.; 
   adc_offset[ADC_Ish ] = 0.;
   adc_offset[ADC_Vt  ] = 0.;
   adc_offset[ADC_Icc ] = 0.;
   adc_offset[ADC_Idd ] = 0.;

   vcc_scale=1.;
   vdd_scale=1.;


   // wb:
   pre_access_timeout = 5; // wb: sec
   post_access_timeout = 5; // wb: sec

}

FPGAControl::~FPGAControl()
{
   

}

/////////////////////////////////////////////////////////////////////////////
// FPGAControl Member Functions
//

// all addresses are (BASEADDRESS | (instruction << 4))
// BASEADDRESS = 0x aa000000 instruction = 0x 000000ii
// address = 0x aa000ii0
// this means ignore the two most and one least sig hex digit
// to read the instruction number

int FPGAControl::SetFreq(float freq)
{
   long nvalue, mvalue;

   if (verbose) *log << "SetFreq: " << freq << endl ;

   if(freq < FREQMIN || freq > FREQMAX){
      return 1;
   }else{
      if(freq > 100){
         nvalue = 1; // n~ = 4
         mvalue = long(2*freq*0.8); // mvalue =n~/2*freq
      }else if(freq > 50){
         nvalue = 2; // n~ = 8
         mvalue = long(4*freq*0.8); // long type cast truncates
      }else if(freq > 25){
         nvalue = 3; // n~ =16
         mvalue = long(8*freq*0.8);
      }/*else{
         //freq out of range
         }*/
   }

   UINT32 value;

   if (baseAddress) {
      value = ((nvalue << 9) | mvalue);
      VME_WRITE(_SetFreq,0,SetFreq,value);
      //if (verbose) log << "Done." << endl ;
      return 0;
   }
   else {
      return -1;
   }
}

int FPGAControl::SetFreq(long nvalue, long mvalue)
{
   UINT32 value;
   if(baseAddress)
   {

      if (verbose)
         *log << "SetFreq: " << nvalue << " " << mvalue << endl ;

      value = ((nvalue << 9) | mvalue);
      VME_WRITE(_SetFreq,0,SetFreq,value);

      return 0;
   }else{
      return -1;
   }
}

int FPGAControl::SetFreq(long tvalue, long nvalue, long mvalue)
{
   UINT32 value;
   if(baseAddress)
   {

      if (verbose)
         *log << "SetFreq: " << tvalue  << " "
              << nvalue << " " << mvalue << endl ;
      value = ((tvalue << 11) | (nvalue << 9) | mvalue);
      VME_WRITE(_SetFreq,0,SetFreq,value);

      return 0;
   }else{
      return -1;
   }
}

int FPGAControl::LoadTriggerNum(long triggerNum)
{
   if(baseAddress){

      if (verbose) 
         *log << "LoadTriggerNum: " << triggerNum << endl ;
      
      VME_WRITE(_NumTrig,BUSY,LoadTriggerNum,triggerNum);

      return 0;
   }else{
      return -1;
   }
}

int FPGAControl::ResetSimMem()
{
   if(baseAddress)
   {
      if (verbose) *log << "ResetSimMem: " << endl ;

      VME_WRITE(_ResetSimMem,TV_BUSY,ResetSimMem,0);

      return 0;
   }else{
      return -1;
   }
}

int FPGAControl::ClearHistoMem()
{
   if(baseAddress)
   {
      if (verbose) *log << "ClearHistoMem: " << endl ;
      VME_WRITE(_ClearHistoMem,HST_BUSY,ClearHistoMem,0);
      return 0;
   }else{
      return -1;
   }
}

unsigned long FPGAControl::ReadHistoMem() {
   UINT32 value;
   if(baseAddress) {

      if ( verbose ) *log << "ReadHistoMem : ..." << endl;
      VME_READ(_ReadHistoMem,HST_BUSY,ReadHistoMem,value);
      if ( verbose ) *log << "..." << value << endl;

      return value;
   }else{
      return 0xffffffff;
   }
}

int FPGAControl::LoadHistoBaseAddr(long value)
{
   if(baseAddress) {

      if (verbose) *log << "LoadHistoBaseAddr: " << value << endl ;
      VME_WRITE(_HistoBaseAddr,HST_BUSY,LoadHistoBaseAddr,value);

      return 0;
   }else{
      return -1;
   }
}

int FPGAControl::SendTV()
{
   if(baseAddress) {
      // just to be on the safe side all memory pointers will be reset
      // before execution of instruction set
      ResetTVMem();
      ResetSimMem();

      ResetOutResyncFIFO();
      
      if (verbose) *log << "SendTV: " << endl ;
      VME_WRITE(_SendTV,TV_BUSY,SendTV,0);

      return 0;
   }else{
      return -1;
   }
}

int FPGAControl::SendTVnowait()
{
   if(baseAddress) {
      // just to be on the safe side all memory pointers will be reset
      // before execution of instruction set
      ResetTVMem();
      ResetSimMem();

      ResetOutResyncFIFO();
      
      if (verbose) *log << "SendTVnowait: " << endl ;
	  *_SendTV = 0;
//      VME_WRITE(_SendTV,TV_BUSY,SendTV,0);

      return 0;
   }else{
      return -1;
   }
}

int FPGAControl::WriteTVMem(long value)
{
   if(baseAddress) {
      if (verbose) *log << "WriteTV: " << value << endl ;

      VME_WRITE(_WriteTVMem,TV_BUSY,WriteTVMem,value);

      return 0;
   }else{
      return -1;
   }
}

int FPGAControl::ResetTVMem()
{
   if(baseAddress) {
      if (verbose) *log << "ResetTVMem: " << endl ;
      VME_WRITE(_ResetTVMem,TV_BUSY,ResetTVMem,0);
      return 0;
   }else{
      return -1;
   }
}

int FPGAControl::WriteSimMem(long value)
{
   if(baseAddress)
   {
      if (verbose) *log << "WriteSimMem: " << value << endl ;
      VME_WRITE(_WriteSimMem,TV_BUSY,WriteSimMem,value);

      return 0;
   }else{
      return -1;
   }
}

int FPGAControl::ResetOutFIFO()
{
   if(baseAddress)  {
      if (verbose) *log << "ResetOutFIFO: " << endl ;
      VME_WRITE(_ResetOutFIFO,TV_BUSY,ResetOutFIFO,0);
      return 0;
   }else{
      return -1;
   }
}

long FPGAControl::ReadOutFIFO()
{
   UINT32 value;
   if(baseAddress) {
      if (verbose) *log << "ReadOutFIFO: ..." << flush;
      VME_READ(_ReadOutFIFO,TV_BUSY,ReadOutFIFO,value);
      if (verbose) *log << "..." << value << endl ;
      return long(value);
   }else{
      return -1;
   }
}

int FPGAControl::SendTriggers()
{
   volatile int ntry;

   if(baseAddress) {
      
      if (verbose) *log << "SendTriggers: " << endl ;
      if ( Lock(MTX_VME) ) 
	 *log << "** ERROR ** SendTriggers: Could not get the MuTeX" << endl;
      for (ntry=0; QueryBoardX(HST_BUSY) && ntry<MxTRY;ntry++ );
      *_SendTrig=0;
      UnLock(MTX_VME);

      return 0;
   }else{
      return -1;
   }
}

long FPGAControl::QueryBoard(unsigned long msk)
{
   UINT32 value;
   //instruction one
   // read at address 1
   if(baseAddress) {
      if ( Lock(MTX_VME) ) 
	 *log << "** ERROR ** QueryBoard: Could not get the MuTeX" << endl;
      value = *_QueryBoard;
      UnLock(MTX_VME);
      if (verbose) *log << "QueryBoard: " << hex << value << dec << endl ;
      return long( (value & msk) );
   }
   else {
      return -1;
   }
}

long FPGAControl::QueryBoardX(unsigned long msk)
{
   UINT32 value;
   //instruction one
   // read at address 1
   if(baseAddress) {
      value = *_QueryBoard;
      if (verbose) 
	 *log << "QueryBoardX: " << hex << value << dec << endl ;
      return long(value & msk);
   }
   else {
      return -1;
   }
}

int FPGAControl::LoadTrigSpacing(long spacing)
{
   if(baseAddress){

      if (verbose) *log << "LoadTrigSpacing: " << spacing << endl ;
      VME_WRITE(_TrigSpacing,HST_BUSY,LoadTrigSpacing,spacing);

      return 0;
   }else{
      return -1;
   }
}


int FPGAControl::EnableStrobe()
{
   if(baseAddress){
      if (verbose) *log << "EnableStrobe: " << endl ;
      VME_WRITE(_EnableStrobe,HST_BUSY,EnableStrobe,1);

      return 0;
   }else{
      return -1;
   }
}

int FPGAControl::DisableStrobe()
{
   if(baseAddress){
      if (verbose) { *log << "DisableStrobe: " << endl ; }
      VME_WRITE(_EnableStrobe,HST_BUSY,DisableStrobe,0);

      //if (verbose) log << "Done. " << endl ;
      return 0;
   }else{
      return -1;
   }
}


int FPGAControl::EnableInpRegPulse()
{
   if(baseAddress){
      if (verbose) *log << "EnableInpRegPulse: " << endl ;
      VME_WRITE(_EnableStrobe,HST_BUSY,EnableInpRegPulse,4);

      return 0;
   }else{
      return -1;
   }
}

int FPGAControl::DisableInpRegPulse()
{
	// same call disables everything
	return DisableStrobe();
}


int FPGAControl::SetDAC(int DACaddress, int value)
{
	*log << " setting address = " << hex << DACaddress 
		<< " with value " << dec << value << endl;
   if(baseAddress){
      UINT32 val = (DACaddress << 16) | value;
      if (verbose) {
         *log << "SetDAC: " << hex << DACaddress << dec << " " <<
            value << endl ; }
      VME_WRITE(_SetDAC,DAC_BUSY,SetDAC,val);

      return 0;
   }else{
      return -1;
   }
   return 0;
}

long FPGAControl::ReadADC(int ADCaddress,int byPassWait)
{
   long value;
   if (verbose) *log << "ReadADC: " << endl ;
   StartADCConversion(ADCaddress,byPassWait);
//   Sleep(200);
   value = ReadADCValue(byPassWait);
   return value;
}

int FPGAControl::StartADCConversion(int ADCaddress, int byPassWait)
{
   if(baseAddress){
//         ADCaddress &= 7L;

      if (verbose) *log << "StartADCConvertion: " << ADCaddress << endl ;
      if (byPassWait) {
         Sleep(10);
         *_StartConvADC = ADCaddress;
         Sleep(10);
         *_StartConvADC = ADCaddress;
         Sleep(10);
      }
      else  {
	 VME_WRITE(_StartConvADC,DAC_BUSY,StartADCConversion,ADCaddress);
	 VME_WRITE(_StartConvADC,DAC_BUSY,StartADCConversion,ADCaddress);
      }
      return 0;
   }
   else
      return -1;
}

long FPGAControl::ReadADCValue(int byPassWait)
{

   UINT32 value = 0x0l;

   if(baseAddress){

      if (byPassWait) {
         Sleep(10);
         value = *_ReadADC;
         Sleep(10);
      }
      else {
	 VME_READ(_ReadADC,DAC_BUSY,ReadADCValue,value);
      }
      if (verbose) *log << "ReadADCValue: " << value << endl ;
      return (long) value;
   }else{
      return -1;
   }
}

int FPGAControl::LoadStrobe2TrigDelay(long delay)
{
   
   if(baseAddress){
      UINT32 val;
      if (verbose) *log << "LoadStrobe2TrigDelay: " << delay << endl ;
      val = (delay & 0xff);
      VME_WRITE(_Strobe2Trig,BUSY,LoadStrobe2TrigDelay,val);

      return 0;
   }else{
      return -1;
   }
   return 0;
}

int FPGAControl::LoadTestVector( const char *ifile) {
   int i,count = 0;
   long dataValue=0;
   if ( ifile==0 ) return count;
   ifstream fIn(ifile);
   if ( fIn.fail() ){
      cout << "Could not open test vector file " << ifile << endl;
      return count;
   }
   if (verbose) *log << "LoadTestVector:" << endl ;
   ResetTVMem();
   for(i=0;i<20;i++) WriteTVMem(0x0);
   do {
      fIn >> hex >> dataValue;
      if ( fIn.fail() ) break;
      WriteTVMem(dataValue);
      count++;
   } while ( fIn.good() );

   for (i=0;i<10;i++)
      WriteTVMem(0x20000); // write the end flag
   ResetTVMem();
   fIn.close();
   return count;
}

int FPGAControl::LoadSimVector(const char *ifile) {
   int count = 0;
   long dataValue=0;
   if ( ifile==0 ) return count;
   ifstream fIn(ifile);
   if ( fIn.fail() ){
      cout << "Could not open test vector file " << ifile << endl;
      return count;
   }

   if (verbose) *log << "LoadSimVector:" << endl ;
   ResetSimMem();
   do {
      fIn >> hex >> dataValue;
      if ( fIn.fail() ) break;
      WriteSimMem(dataValue);
      count++;
   } while ( fIn.good() );
   WriteSimMem(0x8000);
   // reseting pointer after writes
   ResetSimMem();
   fIn.close();
   return count;
}

int FPGAControl::LoadTunedSimVector(long *data, int length )
{
   int count = 0;

   if (verbose) *log << "LoadTunedSimVector:" << endl;

   ResetSimMem();
   while( count < length )
   {
	   WriteSimMem( data[count] );
	   count++;
   }

   WriteSimMem(0x8000);
   // reseting pointer after writes
   ResetSimMem();
   return count;
}


int FPGAControl::TVDiffLocation()
{
   if(baseAddress){
      UINT32 value;
      VME_READ(_TVdiffLoc,TV_BUSY,TVDiffLocation,value);

      if (verbose) *log << "TVDiffLocation: "<< value << endl ;
      return value;
   }else{
      return -1;
   }
}
int FPGAControl::TVDiffWord()
{
   if(baseAddress){
      UINT32 value;
      VME_READ(_TVdiffWord,TV_BUSY,TVDiffWord,value);
      if (verbose) *log << "TVDiffWord: "<< value << endl ;

      return value;
   }else{
      return -1;
   }
}

int FPGAControl::ResetOutResyncFIFO()
{
   if(baseAddress){
      if (verbose) *log << "ResetOutResyncFIFO:" << endl ;
      VME_WRITE(_ResetOutResyncFIFO,TV_BUSY,ResetOutResyncFIFO,0);

      return 0;
   }else{
      return -1;
   }
}

void FPGAControl::ClearDACs() {
// Set to 0 all the values
   SetDAC(0x78,0);
   SetDAC(0x79,0);
   SetDAC(0x7a,0);
   SetDAC(0x7b,0);
   SetDAC(0x7c,0);
   SetDAC(0x7d,0);
   SetDAC(0x7e,0);
   SetDAC(0x7f,0);
   SetDAC(0x70,0);
   SetDAC(0x71,0);
   SetDAC(0x72,0);
   SetDAC(0x73,0);
   SetDAC(0x74,0);
   SetDAC(0x75,0);
   SetDAC(0x76,0);
   SetDAC(0x77,0);
   SetDAC(0x68,0);
   SetDAC(0x69,0);
   SetDAC(0x6a,0);
   SetDAC(0x6b,0);
   SetDAC(0x6c,0);
   SetDAC(0x6d,0);
   SetDAC(0x6e,0);
   SetDAC(0x6f,0);
   SetDAC(0x60,0);
   SetDAC(0x61,0);
   SetDAC(0x62,0);
   SetDAC(0x63,0);
   SetDAC(0x64,0);
   SetDAC(0x65,0);
   SetDAC(0x66,0);
   SetDAC(0x67,0);
   SetDAC(0x58,0);
   SetDAC(0x59,0);
   SetDAC(0x5a,0);
   SetDAC(0x5b,0);
   SetDAC(0x5c,0);
   SetDAC(0x5d,0);
   SetDAC(0x5e,0);
   SetDAC(0x5f,0);
   SetDAC(0x50,0);
   SetDAC(0x51,0);
   SetDAC(0x52,0);
   SetDAC(0x53,0);
   SetDAC(0x54,0);
   SetDAC(0x55,0);
   SetDAC(0x56,0);
   SetDAC(0x57,0);
   SetDAC(0x48,0);
   SetDAC(0x49,0);
   SetDAC(0x4a,0);
   SetDAC(0x4b,0);
   SetDAC(0x4c,0);
   SetDAC(0x4d,0);
   SetDAC(0x4e,0);
   SetDAC(0x4f,0);
   SetDAC(0x40,0);
   SetDAC(0x41,0);
   SetDAC(0x42,0);
   SetDAC(0x43,0);
   SetDAC(0x44,0);
   SetDAC(0x45,0);
   SetDAC(0x46,0);
   SetDAC(0x47,0);
   SetDAC(0x38,0);
   SetDAC(0x39,0);
   SetDAC(0x3a,0);
   SetDAC(0x3b,0);
   SetDAC(0x3c,0);
   SetDAC(0x3d,0);
   SetDAC(0x3e,0);
   SetDAC(0x3f,0);

}

void FPGAControl::SetDACs() {
//   int i;

   ClearDACs();
// Program the default values
   SetDAC(CLK0_high ,0x114 );
   SetDAC(CLK0_low  ,0x0d8 );
   SetDAC(CLK0B_high,0x114 );
   SetDAC(CLK0B_low ,0x0d8 );
   SetDAC(CLK1_high ,0x114 );
   SetDAC(CLK1_low  ,0x0d8 );
   SetDAC(CLK1B_high,0x114 );
   SetDAC(CLK1B_low ,0x0d8 );
   SetDAC(COM0_high ,0x114 );
   SetDAC(COM0_low  ,0x0d8 );
   SetDAC(COM0B_high,0x114 );
   SetDAC(COM0B_low ,0x0d8 );
   SetDAC(COM1_high ,0x114 );
   SetDAC(COM1_low  ,0x0d8 );
   SetDAC(COM1B_high,0x114 );
   SetDAC(COM1B_low ,0x0d8 );
   SetDAC(TOKENIN0_high ,0x1ae );
   SetDAC(TOKENIN0_low  ,0x185 );
   SetDAC(TOKENIN0B_high,0x1ae );
   SetDAC(TOKENIN0B_low ,0x185 );
   SetDAC(TOKENIN1_high ,0x1ae );
   SetDAC(TOKENIN1_low  ,0x185 );
   SetDAC(TOKENIN1B_high,0x1ae );
   SetDAC(TOKENIN1B_low ,0x185 );
   SetDAC(DATAIN0_high ,0x1ae );
   SetDAC(DATAIN0_low  ,0x185 );
   SetDAC(DATAIN0B_high,0x1ae );
   SetDAC(DATAIN0B_low ,0x185 );
   SetDAC(DATAIN1_high ,0x1ae );
   SetDAC(DATAIN1_low  ,0x185 );
   SetDAC(DATAIN1B_high,0x1ae );
   SetDAC(DATAIN1B_low ,0x185 );
   SetDAC(CLK0_width   ,0x0f0 );
   SetDAC(CLK0_delay   ,0x0f0 );
   SetDAC(CLK0_delay   ,0x0f0 );
   SetDAC(LED_thr_high      ,0x100 );
   SetDAC(LED_thr_low       ,0x100 );
   SetDAC(DATAOUT0_thr_high ,0x19a );
   SetDAC(DATAOUT0_thr_low  ,0x19a );
   SetDAC(DATAOUT1_thr_high ,0x19a );
   SetDAC(DATAOUT1_thr_low  ,0x19a );
   SetDAC(TOKENOUT0_thr_high,0x19a );
   SetDAC(TOKENOUT0_thr_low ,0x19a );
   SetDAC(TOKENOUT1_thr_high,0x19a );
   SetDAC(TOKENOUT1_thr_low ,0x19a );

   SetDAC(VCC_dac,0x2cc );
   SetDAC(VDD_dac,0x334 );

}


void FPGAControl::SetDACs(float vcc, float vdd, float frequency)
{
   ClearDACs();   

   // reset the voltages after zeroing out everything
   SetDAC( VDD_dac, (int) ( vdd / 0.001 / 4.883 ) );
   SetDAC( VCC_dac, (int) ( vcc / 0.001 / 4.883 ) );

   // Adjust levels with vdd
   // We first assign the adjusted values to the WfScanConfig components
   // so that they will appear in the configuration tab.

   // TOKEN and DATA lines
   float input_val_hi = vdd / 2.0f + 0.1f;
   float input_val_lo = vdd / 2.0f - 0.1f;
   long input_hi = (int) ( input_val_hi / 0.001f / 4.883f );
   long input_lo = (int) ( input_val_lo / 0.001f / 4.883f );



   // set up the window comparators, LED signal is special
   float w_hi_led_val = vdd * 0.29f + 0.375f;
   float w_lo_led_val = vdd * 0.29f - 0.375f;
   long w_hi_led = (int) ( w_hi_led_val / 0.001 / 4.883 );
   long w_lo_led = (int) ( w_lo_led_val / 0.001 / 4.883 );
   
   float w_hi_val = vdd / 2.0f + 0.1f;
   float w_lo_val = vdd / 2.0f - 0.1f;
   long w_hi = (int) ( w_hi_val / 0.001 / 4.883 );
   long w_lo = (int) ( w_lo_val / 0.001 / 4.883 );
   

   SetDAC(CLK0_high ,0x114 );
   SetDAC(CLK0_low  ,0x0d8 );
   SetDAC(CLK0B_high,0x114 );
   SetDAC(CLK0B_low ,0x0d8 );
   SetDAC(CLK1_high ,0x114 );
   SetDAC(CLK1_low  ,0x0d8 );
   SetDAC(CLK1B_high,0x114 );
   SetDAC(CLK1B_low ,0x0d8 );
   SetDAC(COM0_high ,0x114 );
   SetDAC(COM0_low  ,0x0d8 );
   SetDAC(COM0B_high,0x114 );
   SetDAC(COM0B_low ,0x0d8 );
   SetDAC(COM1_high ,0x114 );
   SetDAC(COM1_low  ,0x0d8 );
   SetDAC(COM1B_high,0x114 );
   SetDAC(COM1B_low ,0x0d8 );

   SetDAC(TOKENIN0_high ,input_hi);
   SetDAC(TOKENIN0_low  ,input_lo); 
   SetDAC(TOKENIN0B_high,input_hi); 
   SetDAC(TOKENIN0B_low ,input_lo);
   SetDAC(TOKENIN1_high ,input_hi);
   SetDAC(TOKENIN1_low  ,input_lo);  
   SetDAC(TOKENIN1B_high,input_hi);  
   SetDAC(TOKENIN1B_low ,input_lo);  

   SetDAC(DATAIN0_high , input_hi);  
   SetDAC(DATAIN0_low  , input_lo); 
   SetDAC(DATAIN0B_high, input_hi); 
   SetDAC(DATAIN0B_low , input_lo);
   SetDAC(DATAIN1_high , input_hi);
   SetDAC(DATAIN1_low  , input_lo);  
   SetDAC(DATAIN1B_high, input_hi);  
   SetDAC(DATAIN1B_low , input_lo);


   // Set the clocks
// OLD formula
//   int iclk = int((0xd2-0x28)*40.0/frequency + 0x28);
// new formula, after adjusting for 0.1 V change everywhere
//   int iclk = int((0xd2-0x28)*40.0/frequency + 0x50);
   int iclk = int((0xf2-0x28)*40.0/frequency + 0x28);

   SetDAC(CLK0_width ,iclk );
   SetDAC(CLK0_delay ,iclk );
   SetDAC(CLK1_width ,iclk ); 
   SetDAC(CLK1_delay ,iclk ); 
   // 0.1 V is the minimum voltage
   SetDAC(COM0_width ,(long) ( 0.1 / 0.001 / 4.883 ) );
   SetDAC(COM0_delay ,(long) ( 0.1 / 0.001 / 4.883 ) );
   SetDAC(COM1_width ,(long) ( 0.1 / 0.001 / 4.883 ) );
   SetDAC(COM1_delay ,(long) ( 0.1 / 0.001 / 4.883 ) );

   SetDAC(LED_thr_high      ,w_hi_led  );  
   SetDAC(LED_thr_low       ,w_lo_led  );  
   SetDAC(DATAOUT0_thr_high ,w_hi);  
   SetDAC(DATAOUT0_thr_low  ,w_lo); 
   SetDAC(DATAOUT1_thr_high ,w_hi); 
   SetDAC(DATAOUT1_thr_low  ,w_lo);  
   SetDAC(TOKENOUT0_thr_high,w_hi);
   SetDAC(TOKENOUT0_thr_low ,w_lo);
   SetDAC(TOKENOUT1_thr_high,w_hi);  
   SetDAC(TOKENOUT1_thr_low ,w_lo);  

   SetDAC(TOKENIN0_width,(long) ( 0.1 / 0.001 / 4.883 ));
   SetDAC(TOKENIN0_delay,(long) ( 0.1 / 0.001 / 4.883 ));
   SetDAC(TOKENIN1_width,(long) ( 0.1 / 0.001 / 4.883 ));
   SetDAC(TOKENIN1_delay,(long) ( 0.1 / 0.001 / 4.883 ));
   SetDAC(DATAIN0_width ,(long) ( 0.1 / 0.001 / 4.883 ));
   SetDAC(DATAIN0_delay ,(long) ( 0.1 / 0.001 / 4.883 ));
   SetDAC(DATAIN1_width ,(long) ( 0.1 / 0.001 / 4.883 ));
   SetDAC(DATAIN1_delay ,(long) ( 0.1 / 0.001 / 4.883 ));


   // Adjust latching
   long cdc_val = (int)(clock_latch[0] +
			(clock_latch[1] + clock_latch[2]/frequency)/
			clock_latch[3]);
   SetDAC(0x6d,cdc_val); // wb: what are 0x6d & 0x6f DACs ?
   SetDAC(0x6f,cdc_val);
   
}

void FPGAControl::SetThreshold(int lvl, float center, float halfwidth) {

   if ( lvl<TOKENOUT1 || lvl>CLK1_B) return;
   float input_val_hi = center + halfwidth;
   float input_val_lo = center - halfwidth;
   long  input_hi     = (long) ( input_val_hi / 0.001 / 4.883 );
   long  input_lo     = (long) ( input_val_lo / 0.001 / 4.883 );

   if( input_lo < 0 )input_lo = 0;
   
   SetDAC(lvl  ,input_hi);
   SetDAC(lvl+1,input_lo);
}

void FPGAControl::SetDelay ( int nSig, float value ){

	long input = (long) ( value / 0.001 / 2.441 );
//	cout << "

	SetDAC( nSig  , input );
	SetDAC( nSig+1, input );
}

void FPGAControl::SetClockLatchDAC( float frequency ) {
   long cdc_val = (int)(clock_latch[0] +
                        (clock_latch[1] + clock_latch[2]/frequency)/
                        clock_latch[3]);
   SetDAC(0x6d,cdc_val);
   SetDAC(0x6f,cdc_val);
}

void  FPGAControl::SetClockLatch( float *ltch) {
   int i;
   if ( ltch==0 ) return;
   for (i=0;i<4;i++) 
      clock_latch[i] = ltch[i];
}

void  FPGAControl::SetADCConversion( float *ltch) {
   int i;
   if ( ltch==0 ) return;
   for (i=0;i<8;i++) 
      adc_conversion[i] = ltch[i];
}

void  FPGAControl::SetADCOffset( float *ltch) {
   int i;
   if ( ltch==0 ) return;
   for (i=0;i<8;i++) 
      adc_offset[i] = ltch[i];
}

void FPGAControl::SetVcc(float vcc) {
   SetDAC(VCC_dac,int(vcc_scale*vcc/4.883e-3f));
}
void FPGAControl::SetVdd(float vdd) {
   SetDAC(VDD_dac,int(vdd_scale*vdd/4.883e-3f));
}
void FPGAControl::SetChipVoltages(float vcc,float vdd) {
   SetDAC(VCC_dac,int(vcc_scale*vcc/4.883e-3f));
   SetDAC(VDD_dac,int(vdd_scale*vdd/4.883e-3f));
}


int  FPGAControl::EnablePinDriver(bool doit) {
   if (baseAddress) {
      if (verbose) *log << "EnablePinDriver " << doit << endl ;
      VME_WRITE(_enablePinDriver,0,EnablePinDriver,doit ? 0 : 1);
      return 0;
   }else{
      return -1;
   }
}


int	FPGAControl::SetHitMask(int mask_no)
{
   if (baseAddress) {
      if (verbose) *log << "SetHitMask " << mask_no << endl ;
      VME_WRITE(_setHitMask,0,SetHitMask,mask_no);
      return 0;
   }else{
      return -1;
   }
}

int	FPGAControl::GetDataQualityFlag()
{
   UINT32 value;
   if(baseAddress) {
      if (verbose) *log << "GetDataQualityFlag: ..." << flush;
      VME_READ(_readDataFlags,0,GetDataQualityFlag,value);
      if (verbose) *log << "..." << value << endl ;
      return int(value);
   }else{
      return -1;
   }
}


int  FPGAControl::ReadFirmwareDate()
{
   UINT32 value;
   if(baseAddress) {
      if (verbose) *log << "ReadFirmwareDate: ..." << flush;
      VME_READ(_readFirmwareDate,0,ReadFirmwareDate,value);
      if (verbose) *log << "..." << value << endl ;
      return int(value);
   }else{
      return -1;
   }
}


int  FPGAControl::SetHeaderDetect( int line_no ) 
{
   if (baseAddress) {
      if (verbose) *log << "SetHeaderDetect " << line_no << endl ;
      VME_WRITE(_setHeaderDetect,0,SetHeaderDetect,line_no);
      return 0;
   }else{
      return -1;
   }
}



//wb: use with care..
long FPGAControl::GeTPostAccessTimeoutLimit(void) {
   return post_access_timeout ;
}
long FPGAControl::GeTPreAccessTimeoutLimit(void) {
   return pre_access_timeout ;
}

long FPGAControl::SeTPostAccessTimeoutLimit(long t) {
   return (post_access_timeout = t) ;
}
long FPGAControl::SeTPreAccessTimeoutLimit(long t) {
   return (pre_access_timeout = t) ;
}